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ORCID"0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay ..."
Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani (2008)
- Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani:
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2008: 613-619
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