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"A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging."

W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi (1995)

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DOI: 10.1109/ICVD.1995.512146

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi:
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. VLSI Design 1995: 398-402

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