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"1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge ..."

Jingcheng Wang et al. (2020)

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DOI: 10.1109/VLSICIRCUITS18222.2020.9162843

access: closed

type: Conference or Workshop Paper

metadata version: 2022-05-12

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  dblp key:
  - conf/vlsic/WangAZKBS20
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  - https://dblp.org/rec/conf/vlsic/WangAZKBS20
Jingcheng Wang, Hyochan An, Qirui Zhang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester:
1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge Processors. VLSI Circuits 2020: 1-2

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