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"Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT."

C. Lu et al. (2015)

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DOI: 10.1109/VLSIC.2015.7231383

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - https://dblp.org/rec/conf/vlsic/LuLNT15
C. Lu, C. H. Lee, T. Nishimura, A. Toriumi:
Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT. VLSIC 2015: 18-

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