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"A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving ..."
Yuan-Ching Lien (2016)
- Yuan-Ching Lien:
A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration. VLSI Circuits 2016: 1-2
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