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"A 50nA quiescent current asynchronous digital-LDO with PLL-modulated ..."

Yu-Huei Lee et al. (2012)

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DOI: 10.1109/VLSIC.2012.6243848

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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  - conf/vlsic/LeePWCYHCLWYHL12
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  - https://dblp.org/rec/conf/vlsic/LeePWCYHCLWYHL12
Yu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee:
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance. VLSIC 2012: 178-179

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