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"A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with ..."

Chen-Ting Ko et al. (2019)

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DOI: 10.23919/VLSIC.2019.8777946

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

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Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. VLSI Circuits 2019: 164-

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