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"A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE."

Pier Andrea Francese et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502359

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  - conf/vlsic/FranceseCOBMMKK18
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  - https://dblp.org/rec/conf/vlsic/FranceseCOBMMKK18
Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl:
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits 2018: 267-268

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