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"An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL ..."

Mark A. Ferriss et al. (2012)

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DOI: 10.1109/VLSIC.2012.6243847

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-02

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  - conf/vlsic/FerrissPNRPBYSV12
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  - https://dblp.org/rec/conf/vlsic/FerrissPNRPBYSV12
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman:
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177

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