BibTeX record conf/vlsic/ChenLWCLLC16

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@inproceedings{DBLP:conf/vlsic/ChenLWCLLC16,
  author    = {Yen{-}Huei Chen and
               Kao{-}Cheng Lin and
               Ching{-}Wei Wu and
               Wei{-}Min Chan and
               Jhon{-}Jhy Liaw and
               Hung{-}Jen Liao and
               Jonathan Chang},
  title     = {A 16nm dual-port {SRAM} with partial suppressed word-line, dummy read
               recovery and negative bit-line circuitries for low {VMIN} applications},
  booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
               HI, USA, June 15-17, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/VLSIC.2016.7573459},
  doi       = {10.1109/VLSIC.2016.7573459},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/ChenLWCLLC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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