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"A soft error robust 32kb SRAM macro featuring access transistor-less 8T ..."

Jaspal Singh Shah, David Nairn, Manoj Sachdev (2012)

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DOI: 10.1109/VLSI-SOC.2012.6379045

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-06

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  dblp key:
  - conf/vlsi/ShahNS12
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  - https://dblp.org/rec/conf/vlsi/ShahNS12
Jaspal Singh Shah, David Nairn, Manoj Sachdev:
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. VLSI-SoC 2012: 275-278

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