Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"An accurate novel gate-sizing metric to optimize circuit performance under ..."

Zahira Perez, Hector Villacorta, Víctor H. Champac (2018)

> Home

Details and statistics

DOI: 10.1109/VLSI-SOC.2018.8644864

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/PerezVC18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/PerezVC18
Zahira Perez, Hector Villacorta, Víctor H. Champac:
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. VLSI-SoC 2018: 77-82

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.