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"Evaluation of fault tolerant technique based on homogeneous FPGA architecture."

Yuki Nishitani et al. (2012)

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DOI: 10.1109/VLSI-SOC.2012.6379034

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-06

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Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC 2012: 225-230

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