"Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects."

Arkadiy Morgenshtein et al. (2003)

> Home

Details and statistics

DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2004-01-22

- no documents available
- export record
  dblp key:
  - conf/vlsi/MorgenshteinMWK03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/MorgenshteinMWK03
Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC 2003: 99-104

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.