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"Cost reduction of system-level tests with stressed structural tests and SVM."

Jing-Jia Liou et al. (2015)

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DOI: 10.1109/VLSI-SOC.2015.7314412

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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  - conf/vlsi/LiouHCC15
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  - https://dblp.org/rec/conf/vlsi/LiouHCC15
Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen:
Cost reduction of system-level tests with stressed structural tests and SVM. VLSI-SoC 2015: 177-182

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