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"Estimating design time for system circuits."

Cyrus Bazeghi et al. (2007)

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DOI: 10.1109/VLSISOC.2007.4402473

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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  - conf/vlsi/BazeghiMGTR07
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Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau:
Estimating design time for system circuits. VLSI-SoC 2007: 60-65

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