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"An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a ..."

Yi-Chieh Kao, Hung-An Chen, Hsi-Pin Ma (2022)

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DOI: 10.1109/VLSI-DAT54769.2022.9768065

access: closed

type: Conference or Workshop Paper

metadata version: 2022-05-23

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  dblp key:
  - conf/vlsi-dat/KaoCM22
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Yi-Chieh Kao, Hung-An Chen, Hsi-Pin Ma:
An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a Latency of 433 ns. VLSI-DAT 2022: 1-4

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