"An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient ..."

Bo-Wei Chen, Yung-Hui Chung, Chia-Ming Tsai (2021)

> Home

Details and statistics

DOI: 10.1109/VLSI-DAT52063.2021.9427312

access: closed

type: Conference or Workshop Paper

metadata version: 2021-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi-dat/ChenCT21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi-dat/ChenCT21
Bo-Wei Chen, Yung-Hui Chung, Chia-Ming Tsai:
An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique. VLSI-DAT 2021: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.