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"Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology."

Federico A. Altolaguirre, Ming-Dou Ker (2013)

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DOI: 10.1109/VLDI-DAT.2013.6533866

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/vlsi-dat/AltolaguirreK13
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  - https://dblp.org/rec/conf/vlsi-dat/AltolaguirreK13
Federico A. Altolaguirre, Ming-Dou Ker:
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. VLSI-DAT 2013: 1-4

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