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"On logic depth per pipelining stage with power aware flop, wave and hybrid ..."

Priyankar Talukdar (2015)

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DOI: 10.1109/ISVDAT.2015.7208053

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vdat/Talukdar15
Priyankar Talukdar:
On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints. VDAT 2015: 1-6

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