Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori ..."

Rahul Shrestha, Ashutosh Sharma (2018)

> Home

Details and statistics

DOI: 10.1007/978-981-13-5950-7_4

access: closed

type: Conference or Workshop Paper

metadata version: 2019-01-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vdat/ShresthaS18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vdat/ShresthaS18
Rahul Shrestha, Ashutosh Sharma:
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices. VDAT 2018: 37-48

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.