"VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class ..."

Hafizur Rahaman et al. (2012)

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DOI: 10.1007/978-3-642-31494-0_30

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-22

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  - conf/vdat/RahamanMJP12
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Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269

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