"Area optimized CMOS layouts of a 50 Gb/s low power 4: 1 multiplexer."

Vibhor Pareek, Gaurvi Goyal (2015)

Details and statistics

DOI: 10.1109/ISVDAT.2015.7208054

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

a service of  Schloss Dagstuhl - Leibniz Center for Informatics