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"High performance bit-sliced pipelined comparator tree for FPGAs."

Ayan Palchaudhuri, Anindya Sundar Dhar (2016)

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DOI: 10.1109/ISVDAT.2016.8064843

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  - conf/vdat/PalchaudhuriD16
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Ayan Palchaudhuri, Anindya Sundar Dhar:
High performance bit-sliced pipelined comparator tree for FPGAs. VDAT 2016: 1-6

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