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"Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays ..."

Nupur Navlakha et al. (2013)

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DOI: 10.1007/978-3-642-42024-5_37

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-05

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  dblp key:
  - conf/vdat/NavlakhaGBS13
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  - https://dblp.org/rec/conf/vdat/NavlakhaGBS13
Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani, Vineet Sahula:
Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals. VDAT 2013: 312-321

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