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"Approximate Testing of Digital VLSI Circuits using Error Significance ..."

Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka (2020)

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DOI: 10.1109/VDAT50263.2020.9190571

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-06

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Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka:
Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. VDAT 2020: 1-6

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