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"Formalization of VHDL Synthesis Procedure in Higher-Order Logic."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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X. Wang, Edward P. Stabler (1991)

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DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2002-01-03

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  dblp key:
  - conf/tphol/WangS91
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  persistent URL:
  - https://dblp.org/rec/conf/tphol/WangS91
X. Wang, Edward P. Stabler:
Formalization of VHDL Synthesis Procedure in Higher-Order Logic. TPHOLs 1991: 106-120

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last updated on 2002-01-03 12:10 CET by the dblp team

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