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"Efficient Bit-Level Model Reductions for Automated Hardware Verification."

Sergey Tverdyshev, Eyad Alkassar (2008)

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DOI: 10.1109/TIME.2008.11

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/time/TverdyshevA08
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  persistent URL:
  - https://dblp.org/rec/conf/time/TverdyshevA08
Sergey Tverdyshev, Eyad Alkassar:
Efficient Bit-Level Model Reductions for Automated Hardware Verification. TIME 2008: 164-172

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