"Evaluation of energy-efficient latch circuits with hybrid tunneling FET ..."

Tse-Ching Wu et al. (2015)

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DOI: 10.1109/SOCC.2015.7406978

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. SoCC 2015: 339-344

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