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"A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time ..."

Vaibhav Verma et al. (2015)

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DOI: 10.1109/SOCC.2015.7406972

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain:
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. SoCC 2015: 304-309

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