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"A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2."

Jin-Cheol Seo et al. (2012)

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DOI: 10.1109/SOCC.2012.6398380

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  - conf/socc/SeoIYOABK12
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  - https://dblp.org/rec/conf/socc/SeoIYOABK12
Jin-Cheol Seo, Sang-Soon Im, Kwan-Hee Yoon, Seung-Wook Oh, Taek-Joon An, Gi-Yeol Bae, Jin-Ku Kang:
A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. SoCC 2012: 57-60

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