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"A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read ..."

Chao-Kuei Chung et al. (2014)

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DOI: 10.1109/SOCC.2014.6948972

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  - conf/socc/ChungLCJCTCHKHLK14
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  - https://dblp.org/rec/conf/socc/ChungLCJCTCHKHLK14
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. SoCC 2014: 455-462

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