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"Test Generation and Site of Fault for Combinational Circuits Using Logic ..."

Jui-I Tsai, Ching-Cheng Teng, Ching-Hung Lee (2006)

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DOI: 10.1109/ICSMC.2006.384364

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Jui-I Tsai, Ching-Cheng Teng, Ching-Hung Lee:
Test Generation and Site of Fault for Combinational Circuits Using Logic Petri Nets. SMC 2006: 91-96

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