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"Clock tree synthesis for heterogeneous 3-D integrated circuits."

Isuru Daulagala, Ioannis Savidis (2017)

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DOI: 10.1109/SLIP.2017.7974911

access: closed

type: Conference or Workshop Paper

metadata version: 2017-07-18

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Isuru Daulagala, Ioannis Savidis:
Clock tree synthesis for heterogeneous 3-D integrated circuits. SLIP 2017: 1-6

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