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"Systolic Array Implementation of DFT with Reduced Multipliers Using Triple ..."

I. Mamatha et al. (2014)

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DOI: 10.1007/978-3-319-04960-1_28

access: closed

type: Conference or Workshop Paper

metadata version: 2017-11-06

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  dblp key:
  - conf/sirs/MamathaTSB14
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I. Mamatha, Shikha Tripathi, T. S. B. Sudarshan, Nikhil Bhattar:
Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product. SIRS 2014: 311-322

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