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"From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A ..."

Ney Laert Vilar Calazans et al. (2003)

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DOI: 10.1109/SBCCI.2003.1232853

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  - https://dblp.org/rec/conf/sbcci/CalazansMHRMC03
Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara:
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355-

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