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"Level Oriented Formal Model for Asynchronous Circuit Verification and its ..."

Tomoya Kitai et al. (2002)

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DOI: 10.1109/PRDC.2002.1185640

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/prdc/KitaiOYMM02
Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers:
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220

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