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"Power Reduction of Superscalar Processor Functional Units by Resizing ..."

Guadalupe Miñana et al. (2005)

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DOI: 10.1007/11556930_5

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  dblp key:
  - conf/patmos/MinanaGHLC05
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Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar:
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS 2005: 40-48

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