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"Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk ..."

Chih-Hsiang Lin, James B. Kuo (2009)

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DOI: 10.1007/978-3-642-11802-9_17

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Chih-Hsiang Lin, James B. Kuo:
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. PATMOS 2009: 127-135

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