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"UVM-based Verification of a Digital PLL Using SystemVerilog."
Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos (2019)
- Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos:
UVM-based Verification of a Digital PLL Using SystemVerilog. PATMOS 2019: 23-28
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