"Area Efficient Multi-Memristor Bit Cell Design for Resistive Processing ..."

Gaurav R et al. (2024)

> Home

Details and statistics

DOI: 10.1109/IEEECONF63530.2024.10830795

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/nvmts/RUDSRAKBG24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/nvmts/RUDSRAKBG24
Gaurav R, Ujwal Uttarwar, Shreyas Deshmukh, Jayatika Sakhuja, Kunal Randad, Samarth Agarwal, Akshata Koshti, Anmol Biswas, Udayan Ganguly:
Area Efficient Multi-Memristor Bit Cell Design for Resistive Processing Unit-Based Neural Network Training. NVMTS 2024: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.