"Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs."

Chien-Ting Chen et al. (2014)

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DOI: 10.1007/978-3-662-44917-2_15

access: open

type: Conference or Workshop Paper

metadata version: 2018-12-23

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  - conf/npc/ChenHCTKWSL14
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  - https://dblp.org/rec/conf/npc/ChenHCTKWSL14
Chien-Ting Chen, Yoshi Shih-Chieh Huang, Yuan-Ying Chang, Chiao-Yun Tu, Chung-Ta King, Tai-Yuan Wang, Janche Sang, Ming-Hua Li:
Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs. NPC 2014: 169-180

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