Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator."

Ahmed J. Abd El-Maksoud et al. (2021)

> Home

Details and statistics

DOI: 10.1109/NILES53778.2021.9600555

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/niles/El-MaksoudMTAEK21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/niles/El-MaksoudMTAEK21
Ahmed J. Abd El-Maksoud, Abdallah Mohamed, Ahmed Tarek, Amr Adel, Amr Eid, Farida Khaled, Fatma Khaled, Ziad Ibrahim, Eman El Mandouh, Hassan Mostafa:
FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator. NILES 2021: 376-379

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.