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"Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control."

Keiji Kishine et al. (2012)

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DOI: 10.1109/MWSCAS.2012.6292092

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-26

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  - conf/mwscas/KishineIONN12
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  - https://dblp.org/rec/conf/mwscas/KishineIONN12
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura:
Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. MWSCAS 2012: 602-605

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