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"A Low Power, Low Chip Area, Two-stage Current-mode DAC Implemented in CMOS ..."

Jakub Dalecki et al. (2019)

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DOI: 10.23919/MIXDES.2019.8787079

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-16

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  dblp key:
  - conf/mixdes/DaleckiDTF19
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Jakub Dalecki, Rafal Dlugosz, Tomasz Talaska, Gunter Fischer:
A Low Power, Low Chip Area, Two-stage Current-mode DAC Implemented in CMOS 130 nm Technology. MIXDES 2019: 151-156

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