"ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient ..."

Dhruv Gajaria, Tosiron Adegbija (2019)

> Home

Details and statistics

DOI: 10.1145/3357526.3357553

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/memsys/GajariaA19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/memsys/GajariaA19
Dhruv Gajaria, Tosiron Adegbija:
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. MEMSYS 2019: 439-450

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.