"A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based ..."

Satoru Miyasono, Yosuke Moriai, Hiroshi Saito (2014)

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DOI: 10.1109/MCSOC.2014.29

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Satoru Miyasono, Yosuke Moriai, Hiroshi Saito:
A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based Network-on-Chip Architecture. MCSoC 2014: 141-148

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