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"Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power ..."
Henrique Kessler et al. (2022)
- Henrique Kessler
, Murilo Bohlke, Leomar S. da Rosa, Marcelo Schiavon Porto, Vinicius V. Camargo:
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. LASCAS 2022: 1-4
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