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"Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power ..."

Henrique Kessler et al. (2022)

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DOI: 10.1109/LASCAS53948.2022.9789079

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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  - conf/lascas/KesslerBRPC22
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Henrique Kessler, Murilo Bohlke, Leomar S. da Rosa, Marcelo Schiavon Porto, Vinicius V. Camargo:
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. LASCAS 2022: 1-4

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