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"On validating data hold times for flip-flops in sequential circuits."

Sudhakar M. Reddy et al. (2000)

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DOI: 10.1109/TEST.2000.894220

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/itc/ReddyPKMTO00
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  persistent URL:
  - https://dblp.org/rec/conf/itc/ReddyPKMTO00
Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325

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