"Improving Test Chip Design Efficiency via Machine Learning."

Zeye Liu et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ITC44170.2019.9000131

access: closed

type: Conference or Workshop Paper

metadata version: 2020-02-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/itc/LiuHFB19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc/LiuHFB19
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton:
Improving Test Chip Design Efficiency via Machine Learning. ITC 2019: 1-10

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.